The present invention relates, in general, to an integrated circuit and method for biasing an impurity region of an integrated circuit structure. More particularly, the present invention relates to an integrated circuit and method for biasing an epitaxial (EPI) layer to a level substantially equal to a supply voltage (V.sub.CC) level yet exhibiting a high reverse breakdown voltage to negative transients of the V.sub.CC supply.
Traditionally, the accepted method for biasing EPI tubs in bipolar integrated circuits is by connecting them directly to V.sub.CC. However, many integrated circuit applications experience negative transient voltages on the V.sub.CC supply line. For example, in some automotive applications, transients of up to .+-.125 volts may be experienced with source impedances as low as 10 ohms. Similarly, industrial atmospheres, robotics applications and other integrated circuit environments having relatively long supply lead lengths may experience such negative voltage transients.
With negative transient voltages on the V.sub.CC line, direct biasing of the EPI tubs may result in a forward biased diode from the P type substrate, which is nominally tied to a circuit ground potential, to the EPI region. Large negative voltage transients on the V.sub.CC line may therefore result in the destruction of the EPI substrate junction or interconnecting metallization.
One previously utilized method for dealing with negative voltage transients has been to eliminate the possibility of current flow in this forward biased diode from the EPI substrate junction by application of V.sub.CC to a P region to provide a high reverse breakdown voltage diode from V.sub.CC to the EPI region. In many applications, however, it is necessary that the EPI regions be held at a voltage less than one diode voltage from V.sub.CC for example, in power BIMOS circuits where the substrate is essentially V.sub.OUT and may go as high as the level of V.sub.CC. Such circuits may be susceptible to latching should the substrate go to V.sub.CC and inject holes into an EPI region biased below V.sub.CC when a signal path P region within the EPI collects. Latching will occur if this P region collecting has positive phase to the output, that is, collected current turns on the output forcing the substrate to a higher level.